By Mark Michaelis
Discover ways to fast construct strong web functions with C#-Microsoft's most modern cutting edge programming language-using this updated publication.
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Extra info for C# Developer's Headstart
The MIPS64 processor has 32, 64-bit, general-purpose registers for this very reason. The Itanium, Intel’s next generation 64-bit chip, goes a step further and has literally hundreds of registers. 2). There are six, 16-bit, segment registers (CS, DS, ES, FS, GS, SS). There are eight, 32-bit, general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP). There is also a 32-bit error flag register (EFLAGS) to signal problems and a 32-bit instruction pointer (EIP). Advanced memory management functions are facilitated by four system registers (GDTR, LDTR, IDTR, TR) and five mode control registers (CR0, CR1, CR2, CR3, CR4).
The address formed by the sum of the segment and offset addresses corresponds directly to the value that is placed on the processor’s address lines. Now you can get a better idea of why they call it “real” mode. The address of a byte in real mode maps directly to a “real” byte in physical memory. 15 Chapter 1 Memory Management Mechanisms 16 Chapter 1 An address is denoted, in Intel assembly language, by a segment:offset pair. 8. 8 Segment addresses denote a particular memory segment and are always stored in one of the 16-bit segment registers.
15, you will see that CR3 plays a vital role in the address resolution process. If CR3 is corrupt, you can kiss your memory manager goodbye. The other two flags (PCD and PWT) in this register are related to caching and are not directly relevant to the immediate discussion. The CR4 register is used to enable a couple of advanced mechanisms. For example, the PAE flag enables four extra address lines when it is set. This would bring the number of address lines to 36. Note that the PG flag must be set in CR0 in order for PAE to be effective.
C# Developer's Headstart by Mark Michaelis